Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
DAC '84 Proceedings of the 21st Design Automation Conference
A metal and via maskset programmable VLSI design methodology using PLAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Joint (3,k)-regular LDPC code and decoder/encoder design
IEEE Transactions on Signal Processing
Factor graphs and the sum-product algorithm
IEEE Transactions on Information Theory
Codes on graphs: normal realizations
IEEE Transactions on Information Theory
The capacity of low-density parity-check codes under message-passing decoding
IEEE Transactions on Information Theory
Design of capacity-approaching irregular low-density parity-check codes
IEEE Transactions on Information Theory
Analysis of sum-product decoding of low-density parity-check codes using a Gaussian approximation
IEEE Transactions on Information Theory
Joint message-passing decoding of LDPC codes and partial-response channels
IEEE Transactions on Information Theory
IEEE Transactions on Information Theory
Combinatorial constructions of low-density parity-check codes for iterative decoding
IEEE Transactions on Information Theory
Regular and irregular progressive edge-growth tanner graphs
IEEE Transactions on Information Theory
Analysis of low-density parity-check codes for the Gilbert-Elliott channel
IEEE Transactions on Information Theory
Shortened Array Codes of Large Girth
IEEE Transactions on Information Theory
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We describe an efficient, fully-parallel Network of Programmable Logic Array (NPLA)-based realization of iterative decoders for structured LDPC codes. The LDPC codes are developed in tandem with the underlying VLSI implementation technique, without compromising chip design constraints. Two classes of codes are considered: one, based on combinatorial objects derived from difference sets and generalizations of non-averaging sequences, and another, based on progressive edge-growth techniques. The proposed implementation reduces routing congestion, a major issue not addressed in prior work. The operating power, delay and chip-size of the circuits are estimated, indicating that the proposed method significantly outperforms presently used standard-cell based architectures. The described LDPC designs can be modified to accommodate widely different requirements, such as those arising in recording systems, as well as wireless and optical data transmission devices.