Dataflow architecture for EEG patient monitor

Authors:
Weiming Hu
Affiliations:
Honeywell Information Systems, Billerica, MA
Venue:
ACM SIGARCH Computer Architecture News
Year:
1985

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Abstract

Much work is currently directed towards dataflow architectures. Most of the proposed architectures attempt to exploit fine grained parallelism. This paper describes an application specific dataflow architecture which exploits coarse grained parallelism. The application is that of a real-time patient monitor used to display patient data.