Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors

Authors:
Sonia Lopez;Steve Dropsho;David H. Albonesi;Oscar Garnica;Juan Lanchares
Affiliations:
Universidad Comlutense de Madrid, Spain;EPFL, Switzerland;Cornell University, USA;Universidad Comlutense de Madrid, Spain;Universidad Comlutense de Madrid, Spain
Venue:
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
Year:
2007

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Abstract

Resizable caches can tradeoff capacity for access speed to dynamically match the needs of the workload. In single-threaded cores, resizable caches adapt to the phases of the running application. In Simultaneous Multi- Threaded (SMT) cores the caching needs can vary greatly across the number of threads and their characteristics, thus, offering even more opportunities to dynamically adjust cache resources to the workload.