A Phase-Adaptive Approach to Increasing Cache Performance

Authors:
Matthew A. Watkins;Sally A. McKee;Lambert Schaelicke
Affiliations:
Cornell University, USA;Cornell University, USA;Intel Corporation
Venue:
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
Year:
2007

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Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory

Journal of Systems Architecture: the EUROMICRO Journal

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Abstract

Technological advances along with more complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application characteristics. This approach to bridging the processor/memory performance gap has been studied in the past, but most studies used trace-driven simulation and only looked at L1 caches. Given the changes in hardware and software since these seminal studies, we revisit the general approach: we present a transparent, phase-adaptive mechanism for L2 cache block superloading with minimal hardware complexity, evaluating it on a full-system simulator running 23 SPEC CPU2000 applications run to completion using training inputs.