FPGA-Based Lookup Circuit for Session-Based IP Packet Classification

  • Authors:

  • Motasem Abdelghani;Sakir Sezer;Emi Garcia;Jun Mu;Ciaran Toal

  • Affiliations:

  • Queen's University Belfast;Queen's University Belfast;Queen's University Belfast;Queen's University Belfast;Queen's University Belfast

  • Venue:
  • AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
  • Year:
  • 2007

Quantified Score

Hi-index 0.00

Visualization

Abstract

In this paper, we present the architecture and implementation of an FPGA-based lookup circuit for a session-based IP packet classifier. The concept of session-based packet classification is summarized and the difference between the traditional- and sessionbased- classification is discussed. A preliminary hardware based architecture customised for FPGA technology is explored and its implementation using Altera Cyclone II technology is outlined. A detailed circuit analysis is presented.