Bitstream relocation with local clock domains for partially reconfigurable FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
A (fault-tolerant)2 scheduler for real-time HW tasks
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
A bitstream relocation technique to improve flexibility of partial reconfiguration
ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms
Journal of Electronic Testing: Theory and Applications
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The regular structure and addressing scheme for the Virtex-II family of Field Programmable Gate Arrays (FPGAs) allows the relocation of partial bitstreams through direct bitstream manipulation. Our bitstream translation program relocates modules on an FPGA by changing the partial bitstream of the module. To take advantage of relocatable modules, three fault tolerant circuit designs are developed and tested. While operating through a fault, these designs provide support for efficient and transparent replacement of the faulty module with a relocated fault-free module. The architecture of the FPGA and static logic significantly constrain the placement of relocatable modules, especially when a microprocessor is placed on the FPGA.