Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors
Proceedings of the Conference on Design, Automation and Test in Europe
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors
Proceedings of the 50th Annual Design Automation Conference
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Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system and cost-effective reliability improvements. In this paper we present an approach to obtain uncertainty bounds on the error propagation probability (EPP) values used in SER estimation based on an analytical approach. We demonstrate how we can compute EPP values and their uncertainty bounds (variances) by examining the logic gates in a topological order. Comparison of this method with the Monte-Carlo (MC) fault simulation approach confirms the accuracy of the presented technique for both the computed EPP values and uncertainty bounds. Also, this technique is 3-5 orders of magnitude faster than fault simulation.