Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
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Network on Chip architectures are proposed as a so- lution to overcome functional and physical scalability shown by shared bus based MPSoC architecture. Unfor- tunately to implement and efficient communication in- frastructure, the designer has to set a lot of parameters. An exhaustive knowledge of how the chosen settings in- fluence the overall behaviour of the designed system is then mandatory. Aim of this paper is to discuss the re- lationship between the performances of a NoC and its configuration parameters in the case of traffic gener- ated by cache operations (block replacements). We paid special attention to investigate the impact of the serial- ization factor, that was already not clearly assessed in literature for this important case study. A numerical analysis, referring to an actual implementation of the NoC on a state-of-the-art 65nm technological process was performed. The obtained results were used to re- port an energy and execution time exploration over the complete design space of interest.