Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects

Authors:
Dongkook Park;Reetuparna Das;Chrysostomos Nicopoulos;Jongman Kim;N. Vijaykrishnan;Ravishankar Iyer;Chita R. Das
Affiliations:
Pennsylvania State University, University Park, PA;Pennsylvania State University, University Park, PA;Pennsylvania State University, University Park, PA;Pennsylvania State University, University Park, PA;Pennsylvania State University, University Park, PA;Intel Corporation;Pennsylvania State University, University Park, PA
Venue:
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
Year:
2007

Citing 0
Cited 10

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Allocator implementations for network-on-chip routers

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
A practical low-latency router architecture with wing channel for on-chip network

Microprocessors & Microsystems
An improvement of router throughput for on-chip networks using on-the-fly virtual channel allocation

ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Inferring packet dependencies to improve trace based simulation of on-chip networks

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
An abacus turn model for time/space-efficient reconfigurable routing

Proceedings of the 38th annual international symposium on Computer architecture
Packet chaining: efficient single-cycle allocation for on-chip networks

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Proactive circuit allocation in multiplane NoCs

Proceedings of the 50th Annual Design Automation Conference
Ordering circuit establishment in multiplane NoCs

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
PAIS: Parallelism-aware interconnect scheduling in multicores

ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers

Quantified Score

Hi-index	0.00

Visualization

Abstract

The acceleration of video as a key network application, combined with the scaling on-chip interconnect needs of multi-core processors, is driving the need for silicon-compatible high bandwidth low latency optical interconnect. CMOS Photonics is a technology ...