An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Reconfigurable hardware provides multiple functions without greatly increasing the die size of SoCs. Field Programmable Gate Array (FPGA), one type of reconfigurable hardware, is developing rapidly to handle high speed and complex applications. In particular, SRAM-based FPGA can be reconfigured during run-time to provide functionality as needed, thus reducing cost and power consumption. However, the reconfiguration delay time and limited resource on FPGA pose new challenges to many real-time scheduling applications. In order to optimize hardware usage and eliminate the impacts of reconfiguration delay, the scheduling algorithms and resource management mechanisms for reconfigurable SoC have to be re-designed. In this paper, we develop a template-based approach to reuse hardware resources without compromising the reconfiguration and performance constraint. The developed solution makes use of offline generated templates to generate near-optimal schedules during run-time.