Time-predictable computer architecture
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
Worst-case execution time analysis for a Java processor
Software—Practice & Experience
A model based approach for debugging embedded systems in real-time
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
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As real-time systems become more prevalent, there is a need to guarantee that these increasingly complex systems perform as designed. One technique involves a static analysis to place an upper bound on worst-case execution time (WCET). Tools for conducting this analysis typically require the developer to digest assembly opcodes, hexadecimal addresses, and other low-level details in order to make sense of the results. Java-specific processors offer a way out of this complexity. Such processors make Java software more predictable, and as a consequence, timing analysis of a real-time system becomes less computationally intensive. WCET analysis tools based on these processors can thus offer more powerful features at higher levels of abstraction. As proof of this concept, we present a tool for static WCET analysis of Java processors. Our performance measurements show that this tool makes WCET analysis interactive, offering continuous feedback to the developer in the form of back-annotations.