Synthesizing a specification-based monitor for safety requirements
Iranian Journal of Science and Technology, Transaction B: Engineering
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Conventional software Verification and Validation (V&V) approaches for real-time and reactive programs are not practical because applying formal methods is too complex and testing methods are incomplete. It seems runtime verification of programs is a novel approach as a compliment to testing methods. We use Event-based Real-time Logic (ERL) as a specification language in order to simply specify safety properties. By applying aspect-oriented approach to instrumentation, we integrate runtime verification module (i.e. Monitor) with program itself and minimize overhead of runtime verification too. Our proposed method, RVERL, consists of three phases. First, safety properties are extracted from program requirements specification. Second, properties are mapped to timing, functional and deadline aspects which constitute the Monitor. Then it is weaved to the program source code. Third, at the execution time, the Monitor as a wrapper observes program behavior and protects the program against its misbehavior (i.e., property violations). Experiments on Rail Road Crossing problem show that the RVERL reveals all property violations while overhead of runtime verification is just about 4 percent.