Dynamically Restructurable Fault-Tolerant Processor Network Architectures

Authors:
D. K. Pradhan
Affiliations:
Departnment of Electrical and Computer Engineering, University of Massachusetts
Venue:
IEEE Transactions on Computers
Year:
1985

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Abstract

A class of novel fault-tolerant multiprocessor networks is proposed. These networks are restructurable in that they can assume different logical configurations to suit different problem environments. More importantly, this restructuriing capability is not altered even after the occurrence of faults. These networks are novel in that they uniquely combine certain desirable features, including self-routing of messages, dynamic reconfigurability, fault-tolerance, the ability to incorporate incremental extension, as well as the capacity to be partitioned with fault-tolerance. What is important about these fault-tolerant features is that they are built-in as an integral part of the design, and not as done traditionally, by means of redundancy.