Implementation and Performance Evaluation of Computer Families

Authors:
E. A. Snow;D. P. Siewiorek
Affiliations:
Intel Corporation;-
Venue:
IEEE Transactions on Computers
Year:
1981

Citing 4
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Abstract

This correspondence proposes a model using microcycle and memory read pause times to account for variation in performance between members of a computer family. Wben applied to the DEC PDP-11 and IBM S/360-S/370 families, the model explains over 90 percent of the variation. This model is useful for initial family planning, as well as design of individual family members.