Unateness Properties of and-Exclusive-or Logic Circuits
IEEE Transactions on Computers
Minimization of Exclusive or and Logical Equivalence Switching Circuits
IEEE Transactions on Computers
A Systematically Designed Binary Array Processor
IEEE Transactions on Computers
ULM Implicants for Minimization of Univers Logic Module Circuits
IEEE Transactions on Computers
Some Characteristics of Universal Cell Nets
IEEE Transactions on Computers
Fan-In Constrained Tree Networks of Flexibe Cells
IEEE Transactions on Computers
STARAN parallel processor system hardware
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
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Parallel processors with bit-serial processing elements (PE's) usually implement arithmetic functions by a sequence of word-level arithmetic operations; however, basic operations must be specified at the bit level. In this correspondence the possibility of more efficiently implementing a function with a special tailored sequence of bit-serial operations is considered. A general scheme is described for generating efficient programs to implement arbitrary functions on bit-serial-arithmetic processors. This scheme is based on logic design methodology and involves designing a logic network to realize a desired function. The parallel processor is then used to efficiently simulate a set of these networks. Heuristic design algorithms are used to generate the logic networks; several algorithms are described and compared with some benchmark functions. Several efficient PE designs are described and analyzed.