Formal verification of systolic networks using theorem proving techniques (abstract only)
CSC '87 Proceedings of the 15th annual conference on Computer Science
A Stochastic Dynamic Local Search Method for Learning Multiple-Valued Logic Networks
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A relational approach to functional decomposition of logic circuits
ACM Transactions on Database Systems (TODS)
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Recent findings indicate that logic design still constitutes 50 percent of the total design effort, and yet few automated tools are being used in industry. The use of an automated theorem-proving system in the logic design process presents an intriguing addition to traditional design automation tools. This paper deals with the automated synthesis of combinational logic. The method consists of a theorem-proving implementation of a systematic, uniform procedure for the synthesis of an arbitrary switching function. Any multiple-valued (including binary) function can be synthesized in a top-down fashion using the functional blocks of the designer's choice. The method is general enough to allow for the choice of an arbitrary logic system and radix. Additional constraints of modularity, technology dependence, fault tolerance, and others may be imposed upon the design. It may also be possible to accommodate into this approach formal design verification, design for testability, functional level modeling, and formal analysis of race and hazard conditions.