Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
Feedback in asynchronous sequential circuits
FOCS '65 Proceedings of the 6th Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1965)
Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops
IEEE Transactions on Computers
IEEE Transactions on Computers
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An asynchronous unit delay is an n-input n-output asynchronous sequential circuit such that the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. The delay is of significance as a building block for shift register realizations of asynchronous circuits.