PROPAN: A Retargetable System for Postpass Optimisations and Analyses
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Fast Optimal Instruction Scheduling for Single-Issue Processors with Arbitrary Latencies
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
Heuristic chaining in directed acyclic graphs
Computer Languages
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An integer programming model that portrays the architectural features of a class of vector and array processors has been developed. This model is used to produce optimal schedules for low-level-instruction codes of such processors. Optimal schedules are produced for both straight codes and instruction loops. Loop scheduling is separately considered because of special consideration that must be given to the effects of the instructions of consecutive loop iterations on each other that are hidden when static instruction scheduling approach is used. Using the model, a number of experiments have been conducted in optimal scheduling of Cray assembly codes.