VirtualClock: a new traffic control algorithm for packet-switched networks
ACM Transactions on Computer Systems (TOCS)
High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
Quality of service: delivering QoS on the Internet and in corporate networks
Quality of service: delivering QoS on the Internet and in corporate networks
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Insights into mobile multimedia communications
Insights into mobile multimedia communications
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Journal of Parallel and Distributed Computing
QoS provisioning in clusters: an investigation of Router and NIC design
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Packet-mode scheduling in input-queued cell-based switches
IEEE/ACM Transactions on Networking (TON)
MediaWorm: A QoS Capable Router Architecture for Clusters
IEEE Transactions on Parallel and Distributed Systems
Performance Evaluation of Adaptive Routing Algorithms for k-ary-n-cubes
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
Current issues in packet switch design
ACM SIGCOMM Computer Communication Review
A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers
HOTI '02 Proceedings of the 10th Symposium on High Performance Interconnects HOT Interconnects
MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
ATM Input-Buffered Switches with the Guaranteed-Rate Property
ISCC '98 Proceedings of the Third IEEE Symposium on Computers & Communications
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Providing full qos support in clusters using only two VCs at the switches
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
A survey of quality of service in mobile computing environments
IEEE Communications Surveys & Tutorials
IEEE Network: The Magazine of Global Internetworking
The Network Processing Forum switch fabric benchmark specifications: an overview
IEEE Network: The Magazine of Global Internetworking
Journal of Systems and Software
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Virtual channels (VCs) are a popular solution for the provision of quality of service (QoS). Current interconnect standards propose 16 or even more VCs for this purpose. However, most implementations do not offer so many VCs because it is too expensive in terms of silicon area. Therefore, a reduction of the number of VCs necessary to support QoS can be very helpful in the switch design and implementation.In this paper, we show that this number of VCs can be reduced if the system is considered as a whole rather than each element being taken separately. The scheduling decisions made at network interfaces can be easily reused at switches without significantly altering the global behavior. In this way, we obtain a noticeable reduction of silicon area, component count, and, thus, power consumption, and we can provide similar performance to a more complex architecture. We also show that this is a scalable technique, suitable for the foreseen demands of traffic.