Cooling schedules for optimal annealing
Mathematics of Operations Research
Simulated annealing: theory and applications
Simulated annealing: theory and applications
Unsupervised Texture Segmentation in a Deterministic Annealing Framework
IEEE Transactions on Pattern Analysis and Machine Intelligence
Morphologically Constrained GRFs: Applications to Texture Synthesis and Analysis
IEEE Transactions on Pattern Analysis and Machine Intelligence
Histogram clustering for unsupervised segmentation and image retrieval
Pattern Recognition Letters
Markov random field modeling in image analysis
Markov random field modeling in image analysis
Facts, Conjectures, and Improvements for Simulated Annealing
Facts, Conjectures, and Improvements for Simulated Annealing
Stochastic Relaxation, Gibbs Distributions, and the Bayesian Restoration of Images
IEEE Transactions on Pattern Analysis and Machine Intelligence
| Hi-index | 0.01 |
The system-on-chip design of purely digital architectures, which are based on massively parallel Markov random field (MRF) processing principles is so far an unstructured, time consuming, fault-prone and complex task. Up to now a tool-kit is not available to systematically support the VLSI design task in a single coherent environment and along a seamless design flow for various digital semiconductor-technologies. In this contribution, we report on a completely technology-independent and graph-theoretical approach for the VLSI design of massively parallel MRF processing devices. The paper is finalized by selected results, which show generated graphs, synthesis results and prototypical implementations using FPGA technologies. All together these results demonstrate the capability of the proposed graph-theoretical approach and manifest the industrial relevance of the developed tool-kit.