Arbitrated time-to-first spike CMOS image sensor with on-chip histogram equalization

Authors:
Chen Shoushun;Amine Bermak
Affiliations:
Smart Sensory Integrated Systems Laboratory, Electronic and Computer Engineering Department, Hong Kong University of Science and Technology, Kowloon, Hong Kong;Smart Sensory Integrated Systems Laboratory, Electronic and Computer Engineering Department, Hong Kong University of Science and Technology, Kowloon, Hong Kong
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2007

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Abstract

This paper presents a time-to-first spike (TFS) and address event representation (AER)-based CMOS vision sensor performing image capture and on-chip histogram equalization (HE). The pixel values are read-out using an asynchronous handshaking type of read-out, while the HE processing is carried out using simple and yet robust digital timer occupying a very small silicon area (0.1 × 0.6 mm2). Low-power operation (10 nA per pixel) is achieved since the pixels are only allowed to switch once per frame. Once the pixel is acknowledged, it is granted access to the bus and then forced into a stand-by mode until the next frame cycle starts again. Timing errors inherent in AER-type of imagers are reduced using a number of novel techniques such as fair and fast arbitration using toggled priority (TP), higher-radix, and pipelined arbitration. A verilog simulator was developed in order to simulate the effect of timing errors encountered in AER-based imagers. A prototype chip was implemented in AMIS 0.35µm process with a silicon area of 3.1 × 3.2 mm2. Successful operation of the prototype is illustrated through experimental measurements.