IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
This paper presents a test data compression scheme that can be used to further improve compressions achieved by LFSR reseeding. The proposed compression technique can be implemented with very low hardware overhead. Unlike most commercial test data compression tools, the proposed method requires no special ATPG that is customized for the proposed scheme and can be used to compress test patterns generated by any ATPG tool. The test data to be stored in the ATE memory are much smaller than that for previously published schemes and the number of test patterns that need to be generated is smaller than other weighted random pattern testing schemes. Experimental results on a large industry design show that over 1600X compression is achievable by the proposed scheme with the number of patterns comparable to that of highly compacted deterministic patterns.