Implications of Device Timing Variability on Full Chip Timing

Authors:
Murali Annavaram;Ed Grochowski;Paul Reed
Affiliations:
Microarchitecture Research Lab, Intel Corporation, 2200 Mission College Blvd, Santa Clara, CA 95054. murali.m.annavaram@intel.com;Microarchitecture Research Lab, Intel Corporation, 2200 Mission College Blvd, Santa Clara, CA 95054. edward.grochowski@intel.com;Microarchitecture Research Lab, Intel Corporation, 2200 Mission College Blvd, Santa Clara, CA 95054. paul.reed@intel.com
Venue:
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Year:
2007

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Abstract

As process technologies continue to scale, the magnitude of within-die device parameter variations is expected to increase and may lead to significant timing variability. This paper presents a quantitative evaluation of how low level device timing variations impact the timing at the functional block level. We evaluate two types of timing variations: random and systematic variations. The study introduces random and systematic timing variations to several functional blocks in Intel® Core驴 Duo microprocessor design database and measures the resulting timing margins. The primary conclusion of this research is that as a result of combining two probability distributions (the distribution of the random variation and the distribution of path timing margins) functional block timing margins degrade non-linearly with increasing variability.