A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units

  • Authors:

  • Takeshi Shiro;Masaaki Abe;Keishi Sakanushi;Yoshinori Takeuchi;Masaharu Imai

  • Affiliations:

  • Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa;Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa;Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa;Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa;Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa

  • Venue:
  • ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
  • Year:
  • 2007

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper proposes a method for generating a pipeline processor from the behavior description of instructions. In the proposed method, a micro-operation description is generated by complementing the behavior description with specifications of the pipeline stages, such as the number of pipeline stages, the attributes of each stage. From the behavior description, software development tools, such as an instruction-set simulator (ISS), a compiler, and an assembler can be generated, and a synthesizable HDL description of a processor can be generated from the micro-operation description. Compared with the conventional method of writing individual descriptions, the proposed method can dramatically reduce the code size of the architectural description language and the design time without degrading the design quality. As a result, a design space exploration can be performed efficiently.