Deeper Bound in BMC by Combining Constant Propagation and Abstraction

  • Authors:

  • Roy Armoni;Limor Fix;Ranan Fraer;Tamir Heyman;Moshe Vardi;Yakir Vizel;Yael Zbar

  • Affiliations:

  • -;Logic and Validation Technology, Intel Corporation, Haifa, Israel;Logic and Validation Technology, Intel Corporation, Haifa, Israel;Logic and Validation Technology, Intel Corporation, Haifa, Israel/ Carnegie Mellon University, Pitts;Rich University, Houston, Tx;Logic and Validation Technology, Intel Corporation, Haifa, Israel;Logic and Validation Technology, Intel Corporation, Haifa, Israel

  • Venue:
  • ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
  • Year:
  • 2007

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Abstract

The most successful technologies for automatic verification of large industrial circuits are bounded model checking, abstraction, and iterative refinement. Previous work has demonstrated the ability to verify circuits with thousands of state elements achieving bounds of at most a couple of hundreds. In this paper we present several novel techniques for abstraction-based bounded model checking. Specifically, we introduce a constant-propagation technique to simplify the formulas submitted to the CNF SAT solver; we present a new proof-based iterative abstraction technique for bounded model checking; and we show how the two techniques can be combined. The experimental results demonstrate our ability to handle circuit with several thousands state elements reaching bounds nearing 1,000.