Approximation algorithm for data mapping on block multi-threaded network processor architectures
Proceedings of the 44th annual Design Automation Conference
| Hi-index | 0.00 |
The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, and block multi-threading. The paper presents an automated system-level design technique for process mapping on such architectures with an objective of maximizing the worst case throughput of the application. As this mapping must be done in the presence of resource (processors and code size) constraints, this is an NP-complete problem (Ausiello et al., 1999). We present a polynomial time approximation algorithm guaranteed to generate solutions with throughput at least 1/2 that of optimal solutions. The proposed algorithm was utilized to map realistic applications on the Intel IXP2400 (NP) architecture, and produced solutions within 78% of optimal.