Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique

Authors:
Roel Pantonial;Md. Ashfaquzzaman Khan;Naoto Miyamoto;Koji Kotani;Shigetoshi Sugawa;Tadahiro Ohmi
Affiliations:
Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85;Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85;New Industry Creation Hatchery Center, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai,;Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85;Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85;New Industry Creation Hatchery Center, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai,
Venue:
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Year:
2007

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Power minimization for dynamically reconfigurable FPGA partitioning

ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems

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Abstract

This paper studies issues concerning dynamically reconfigurable FPGA (DRFPGA). It reports the architecture and performance of Flexible Processor III (FP3), a newly proposed DRFPGA. The FP3 employs a new shift register-type temporal interconnect to reduce operation delay. Designed and fabricated in 0.35um 2P3M CMOS technology, FP3 works correctly as a multi-context FPGA. Our experimental results show that there exist cases where the best user circuit speed was achieved when 2 contexts were in use for a benchmark circuit. This is because of the reduction of buffers in the critical path by temporal partitioning.