Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses

  • Authors:

  • Fawnizu Azmadi Hussin;Tomokazu Yoneda;Alex Orailoglu;Hideo Fujiwara

  • Affiliations:

  • Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science Cit;Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science Cit;Computer Science and Engineering Department, University of California, San Diego, La Jolla, CA 92093;Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science Cit

  • Venue:
  • ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
  • Year:
  • 2007

Quantified Score

Hi-index 0.00

Visualization

Abstract

An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed methodology handles both flat bus single processor SOC and hierarchical bus multiprocessor SOC. It is based on a resource graph manipulation and a packet-based packet set scheduling methodology. The resource graph is decomposed into a set of test configuration graphs, which are then used to determine the optimum test configurations and test delivery schedule under a given power constraint. In order to validate the effectiveness of the proposed methodology, a number of experiments are run on several modified benchmark circuits. The results clearly underscore the advantages of the proposed methodology.