Constraint-free analog placement with topological symmetry structure
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Regularity-oriented analog placement with diffusion sharing and well island generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Regularity-constrained floorplanning for multi-core processors
Proceedings of the 2011 international symposium on Physical design
Regularity-constrained floorplanning for multi-core processors
Integration, the VLSI Journal
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This paper introduces a new concept of floorplanning and block placement, called structured placement. Regularity is a key criterion of structured placement so that placement can make progress beyond constraint-driven approaches. This paper formulates the topological regularity that is extractable from a sequence-pair. Regular structures like arrays and rows are defined on a single-sequence that is a kind of standard representation of a sequence-pair. We extract regular structures from a single-sequence in O(n), and then evaluate the structures by quantifying the regularity as an objective function. Besides, we propose a new simulated annealing (SA) framework, called dual SA, where we convey a constructive feature to an SA framework, so that it attains a placement balancing the size of regular structures against the area efficiency. In experiments, we apply our structured placement to analog block designs, and reveal the definite advantage that our placements contain many regular structures such as rows and arrays without increasing the chip area and the wire length, compared to the existing placement.