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Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
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Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
ALS '01 Proceedings of the 5th annual Linux Showcase & Conference - Volume 5
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RAID'05 Proceedings of the 8th international conference on Recent Advances in Intrusion Detection
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IEEE/ACM Transactions on Networking (TON)
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ACM Transactions on Computer Systems (TOCS)
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IEEE/ACM Transactions on Networking (TON)
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Proceedings of the Twenty-Fourth ACM Symposium on Operating Systems Principles
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Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide most of the complexities of efficient program execution, programmers of NPUs face a 'bare-metal' view of the architecture. They have to deal with a multithreaded environment with a high degree of parallelism, pipelining and multiple, heterogeneous, execution units and memory banks. Software development on such architectures is expensive. Moreover, different NPUs, even within the same family, differ considerably in their architecture, making portability of the software a major concern. At the same time expensive network processing applications based on deep packet inspection are both in-creasingly important and increasingly difficult to realize due to high link rates. They could potentially benefit greatly from the hardware features offered by NPUs, provided they were easy to use. We therefore propose to use more abstract programming models that hide much of the complexity of 'bare-metal' architectures from the programmer. In this paper, we present one such programming model: Ruler, a flexible high-level language for deep packet in-spection (DPI) and packet rewriting that is easy to learn, platform independent and lets the programmer concentrate on the functionality of the application. Ruler provides packet matching and rewrit-ing based on regular expressions. We describe our implementa-tion on the Intel IXP2xxx NPU and show how it provides versatile packet processing at gigabit line rates.