A methodology for timing model characterization for statistical static timing analysis

Authors:
Zhuo Feng;Peng Li
Affiliations:
Texas A&M University, College Station, TX;Texas A&M University, College Station, TX
Venue:
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Year:
2007

Citing 13
Cited 1

A gate-delay model for high-speed CMOS circuits

DAC '94 Proceedings of the 31st annual Design Automation Conference
First-order incremental block-based statistical timing analysis

Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions

Proceedings of the 42nd annual Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions

Proceedings of the 42nd annual Design Automation Conference
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model

Proceedings of the 42nd annual Design Automation Conference
An efficient algorithm for statistical minimization of total power under timing yield constraints

Proceedings of the 42nd annual Design Automation Conference
Robust gate sizing by geometric programming

Proceedings of the 42nd annual Design Automation Conference
A robust cell-level crosstalk delay change analysis

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing using incremental parameterized statistical timing analysis

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Efficient VCO phase macromodel generation considering statistical parametric variations

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Quantified Score

Hi-index	0.00

Visualization

Abstract

While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realization of these techniques heavily depends on the availability of timing models that feed the statistical timing analysis engine. To target at this critical but less explored territory, in this paper, we present numerical and statistical modeling techniques that are suitable for the underlying timing model characterization infrastructure of statistical timing analysis. Our techniques are centered around the understanding that while the widening process variability calls for accurate non-first-order timing models, their deployment requires well-controlled characterization techniques to cope with the complexity and scalability. We present a methodology by which timing variabilities in interconnects and nonlinear gates are translated efficiently into quadratic timing models suitable for accurate statistical timing analysis. Specific parameter reduction techniques are developed to control the characterization cost that is a function of number of variation sources. The proposed techniques are extensively demonstrated under the context of logic stage timing characterization involving interactions between logic gates and interconnects.