On an approach in implementing DSP algorithms for digital hearing aids; a noise reduction core case study

  • Authors:

  • Wasit Limprasert;Pasin Israsena;Nitin Afzulpurkar;Lertsak Lekawat

  • Affiliations:

  • Asian Institute of Technology, Klongluang, Pathumthani, Thailand;NECTEC, Pathumthani, Thailand;Asian Institute of Technology, Pathumthani, Thailand;Asian Institute of Technology, Pathumthani, Thailand

  • Venue:
  • Proceedings of the 1st international convention on Rehabilitation engineering & assistive technology: in conjunction with 1st Tan Tock Seng Hospital Neurorehabilitation Meeting
  • Year:
  • 2007

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Abstract

One of the major problems for hearing aid users is surrounding noise. The objective of the project is to design a noise reduction hardware (integrated circuit) for digital hearing aids. Instead of relying on separate algorithm and hardware (integrated circuit) developments, a design flow that integrates the developments of DSP algorithms and FPGA hardware to increase performance and reduce development time is illustrated. A noise reduction core using integrated adaptive beamformer and feedback control is designed and tested as an example.