Time Interpolation: So Many Metrics, So Few Registers

  • Authors:
  • Todd Mytkowicz;Peter F. Sweeney;Matthias Hauswirth;Amer Diwan

  • Affiliations:
  • -;-;-;-

  • Venue:
  • Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
  • Year:
  • 2007
  • Program Metamorphosis

    Genoa Proceedings of the 23rd European Conference on ECOOP 2009 --- Object-Oriented Programming

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Abstract

The performance of computer systems varies over the course of their execution. A system may perform well dur- ing some parts of its execution and poorly during others. To understand why a system behaves in this way performance analysts need to study its time-varying behavior. Fortu- nately, modern microprocessors support hardware perfor- mance monitors which enable performance analysts to col- lect time-varying metrics with relative ease. Unfortunately, even though modern microprocessors can collect hundreds of metrics, they can collect only a few of these metrics si- multaneously. Prior work has proposed time-interpolation techniques for circumventing this limitation. Time interpo- lation collects different metrics at different points in time, either within the same trace (multiplexing) or in different traces (trace alignment), and interpolates the results to al- low reasoning across all metrics at the same points in time. This paper introduces and uses a novel approach for evaluating time interpolation techniques. This evaluation leads to insights that improve both multiplexing and trace- alignment. Specifically, this paper (i) improves the effective- ness and applicability of the best performing trace align- ment technique in prior work; and (ii) introduces criteria that performance analysts can use to determine whether or not to trust multiplexing or trace alignment results for their particular situation. Finally, this paper evaluates time in- terpolation techniques by exploring their performance in a wide variety of situations and on programs written in two different programming languages, C and Java, and on two different architectures, Pentium 4 and POWER4. This work is supported by NSF CSE-0509521, NSF Career CCR- 0133457, DARPA contract HR0011-07-9-0002, and a gift from Intel. Any opinions, findings and conclusions or recommendations expressed in this material are the authors' and do not necessarily reflect those of the spon- sors.