Elements of information theory
Elements of information theory
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Entropy, counting, and programmable interconnect
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Interconnect prediction for programmable logic devices
Proceedings of the 2001 international workshop on System-level interconnect prediction
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Design of Interconnection Networks for Programmable Logic
Design of Interconnection Networks for Programmable Logic
Proceedings of the 2006 international workshop on System-level interconnect prediction
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 65nm flash-based FPGA fabric optimized for low cost and power
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
A non-volatile reconfigurable offloader for wireless sensor nodes
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
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In a cluster-based FPGA, the interconnect from external routing tracks and cluster feedbacks to the LUT inputs consumes significant area, and no consensus has emerged among different implementations (e.g., 1-level or 2-level). In this paper, we model this interconnect as a unified input interconnect block (IIB). We identify three types of IIBs and develop general combinatorial techniques to count the number of distinct functional configurations for them. We use entropy, defined as the logarithm of this count, to estimate an IIB's routing flexibility. This enables us to analytically evaluate different IIBs without the customary time-consuming place and route experiments. We show that both depopulated 1-level IIBs and VPR-style 2-level IIBs achieve high routing flexibility but lack area efficiency. We propose a novel class of highly efficient, yet still simple, IIBs that use substantially fewer switches with only a small degradation in routing flexibility. Experimental results verify the routability of these IIBs, and confirm that entropy is a good predictor of routability.