System-level PVT variation-aware power exploration of on-chip communication architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper, we model on-chip signaling over a bus con- sisting of encoding, drivers, transmission lines, receivers and decoding. We characterize the signaling circuitry as a function of its load capacitance. The effective load ca- pacitance seen by a driver is derived for the decoupling method and distributed RLC transmission line models. The driver delay and rise time corresponding to the derived ef- fective capacitance are used to derive the far-end voltage of a transmission line bus. The effects of process variation are taken into account in the characterization of the sig- naling circuitry and in the wire analysis. The overall delay variation of the bus due to device and wire process varia- tion is then calculated. The model is verified by comparing it to HSPICE. We implement regular voltage mode, level- encoded dual-rail and 1-of-4 signaling circuitry and apply the derived model to analyze them. The implementation and analysis are done in 45 nm technology.