Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design configuration selection for hard-error reliable processors via statistical rules
Microprocessors & Microsystems
| Hi-index | 0.00 |
Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by deterministic glitch elimination (using hazard filtering and path balancing) increases because glitches randomly start reappearing under the influence of process variation. Combining existing techniques, we propose a new statistical mixed integer linear programming (MILP) formulation, which combines glitch elimination and dual-threshold design to statistically minimize the total power in a glitch-free circuit under process variation.