A mechanistic performance model for superscalar out-of-order processors
ACM Transactions on Computer Systems (TOCS)
Data cache-energy and throughput models: design exploration for embedded processors
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Fast modeling of shared caches in multicore systems
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
| Hi-index | 14.98 |
Advances in semiconductor technology enable larger processor design space, leading to increasingly complex systems. Designers must evaluate many architecture design points to achieve the optimal design. Currently, most architecture exploration is performed using cycle accurate simulators. Although accurate, these tools are slow, thus limiting a comprehensive design search. The vast design space of today's complex processors and time to market economic pressures motivate the need for faster architectural evaluation methods. This paper presents a superscalar processor performance model that enables rapid exploration of the architecture design space for superscalar processors. It supplements current design tools by quickly identifying promising areas for more thorough and time consuming exploration with traditional tools. The model estimates instruction throughput of a superscalar processor based on early architectural design parameters and application properties. It has been validated with the Simplescalar out-of-order simulator. The model, which executed 40,000 times faster, produces instruction throughput estimates that are with within 5.5% of the corresponding SimpleScalar values.