Register allocation with instruction scheduling for VLIW-architectures
Programming and Computing Software
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The performance of modern microprocessors considerably depends on the efficient workload of their execution units. The performance in modern applications is considerably affected by instruction stalls. Until recently, the problem of instruction stalls was mainly studied for superscalar microprocessors. A software instruction prefetching method for VLIW/EPIC architectures that makes it possible to improve performance for a certain class of problems is described.