Implementing a parallel matrix factorization library on the cell broadband engine
Scientific Programming - High Performance Computing with the Cell Broadband Engine
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Today, multicore microprocessors are at the heart of systems ranging from laptops to supercomputers. The shift to multicore architectures has transformed the problem of improving program performance from a micro-architecture problem to a software problem, shifting the focus from instruction-level parallelism to thread-level parallelism. As the density of transistors on chips increases, technology roadmaps call for increasing the number of cores. A key challenge facing the community is how we will keep increasing numbers of cores busy with productive work. Of great interest are answers to the question, "Where will all the threads come from" This panel will explore several dimensions of the problem of developing applications that effectively use extensive thread-level parallelism. First, we will hear about an initiative that aims to exploit the growing number of cores by increasing the sophistication of applications that run on the desktop. Next, we will hear about experiences mapping applications to systems with large-scale multithreading using programming models that rely on implicit and/or explicit parallelism. Finally, we will hear about past and present work on languages and compiler technology for mapping programs onto parallel systems. An aim of the panel is to identify promising directions for the future and potential stumbling blocks. The panelists have a broad range of experience with parallel applications, programming models and languages, and compiler technology for mapping languages to parallel architectures.