Survey of ATM switch architectures
Computer Networks and ISDN Systems
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
A High-Performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
Hi-index | 0.00 |
A new algorithm for scheduling the transmission of packets in routers is discussed. The approach takes into account the separation of queues in the input ports of a router and the segmentation of incoming packets into cells. Its main advantage is that, while performing as good as other existing algorithms, its complexity is considerably smaller. The feature that differentiates the algorithm is that it relies on past information in order to avoid processing of all data at every given timeslot, which is a time-consuming process.