Efficient implementation of interpolation technique for symbol timing recovery

  • Authors:

  • Chin-Long Wey;Shin-Yo Lin;Tsung-Han Tsai;Muh-Tian Shiue

  • Affiliations:

  • Department of Electrical Engineering, National Central University, Chung-Li, Taiwan;Department of Electrical Engineering, National Central University, Chung-Li, Taiwan;Department of Electrical Engineering, National Central University, Chung-Li, Taiwan;Department of Electrical Engineering, National Central University, Chung-Li, Taiwan

  • Venue:
  • CEA'07 Proceedings of the 2007 annual Conference on International Conference on Computer Engineering and Applications
  • Year:
  • 2007

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Abstract

This study considers a non-synchronized sampling scheme for symbol timing recovery in DVB-T Transceiver design. The received signal is performed by a fixed sampling clock; the samples are not synchronized to the incoming data symbols. Timing adjustment is done after sampling using interpolation. The Lagrange interpolation for timing adjustment can be implemented FIR filter having changeable coefficients. This interpolation filter can be efficiently implemented using the Farrow structure. Take the advantage of symmetric property of Farrow Structure, the paper presents a low power/low-cost cubic Farrow structure, where the standard cells in TSMC .18µm digial CMOS process were employed. Comparing the conventional Farrow structure, implementing with the same process, the developed structure achieves 36.8% lower power consumption and 24.3% low area cost than the conventional one.