Synthesis of timing scenarios for embedded systems using modular Petri nets

Authors:
Woo Jin Lee;Young Joon Park;Ho Kyoung Lee
Affiliations:
EECS School, Kyungpook National University, Sangyug-dong, Book-gu, Daegu, Korea;EECS School, Kyungpook National University, Sangyug-dong, Book-gu, Daegu, Korea;Network Infra Laboratory of Korea Telecom, Kyungpook National University, Sangyug-dong, Book-gu, Daegu, Korea
Venue:
CEA'07 Proceedings of the 2007 annual Conference on International Conference on Computer Engineering and Applications
Year:
2007

Citing 7
Cited 0

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ANALYSIS OF ASYNCHRONOUS CONCURRENT SYSTEMS BY TIMED PETRI NETS

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Abstract

In developing time-critical systems such as real-time systems and embedded systems, it is important to check timing conflicts between timing requirements as earlier as possible. For checking timing conflicts, at least, a formal notation should be introduced for a concrete and unambiguous requirements specification. However, in an earlier development phase it is not easy to describe timing requirements by using formal methods. In this paper, we propose a systematic procedure for transforming and synthesizing timing scenarios of embedded systems into a Petri net-based model. Although our approach is based on the Petri net formalism, users only focus on describing timing requirements in the scenario concepts, since the detailed transformation and integration procedures based on Petri nets are hidden to users.