Optimization of board-level thermomechanical reliability of high performance flip-chip package assembly

  • Authors:

  • Tong Hong Wang;Ching-Chun Wang;Yi-Shao Lai;Kuo-Chin Chang;Chien-Hsun Lee

  • Affiliations:

  • Central Labs, Advanced Semiconductor Engineering, Inc., 26 Chin 3rd Road, Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan;Central Labs, Advanced Semiconductor Engineering, Inc., 26 Chin 3rd Road, Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan;Central Labs, Advanced Semiconductor Engineering, Inc., 26 Chin 3rd Road, Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan;Taiwan Semiconductor Manufacturing Company, Ltd., 6 Creation Road 2, Hsinchu Science Park, Hsinchu, Taiwan;Taiwan Semiconductor Manufacturing Company, Ltd., 6 Creation Road 2, Hsinchu Science Park, Hsinchu, Taiwan

  • Venue:
  • Microelectronic Engineering
  • Year:
  • 2008

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Abstract

In this paper, we study board-level thermomechanical reliability of a high performance flip-chip ball grid array package assembly subjected to an accelerated thermal cycling test condition. Different control factors are considered for an optimal design towards enhancement of the thermal fatigue resistance of solder joints. These factors include solder composition, underfill, substrate size, lid thickness, stiffener ring width, test board size, soldermask opening on the substrate side, and pad size on the test board. The shape of solder joints after reflow is estimated using Surface Evolver. The optimal design is obtained using an L"1"8 orthogonal array according to the Taguchi optimization method. Importance of these control factors on the board-level thermomechanical reliability of the package is also ranked.