Multithreaded coprocessor interface for multi-core multimedia SoC

Authors:
Shih-Hao Ou;Tay-Jyi Lin;Xiang Sheng Deng;Zhi Hong Zhuo;Chih Wei Liu
Affiliations:
National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan
Venue:
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Year:
2008

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Limits of instruction-level parallelism

ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems

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Abstract

Modern architectures exploit task level parallelism to improve their performance in a cost-effective manner. However, task synchronization and management is time consuming and wastes computing resources especially on application-specific architectures, such as DSP. In this paper, we propose a smart coprocessor interface that helps to offload the task management job from MPU or DSP. In our simulations, our approach can improve the overall performance of a dual-core platform by 57%. The hardware overhead of the interface is only 1.56% of the DSP core.