Non-Gaussian statistical timing models of die-to-die and within-die parameter variations for full chip analysis

Authors:
Katsumi Homma;Izumi Nitta;Toshiyuki Shibuya
Affiliations:
Fujitsu Laboratories Ltd., Nakahara-ku, Kawasaki-shi, Japan;Fujitsu Laboratories Ltd., Nakahara-ku, Kawasaki-shi, Japan;Fujitsu Laboratories Ltd., Nakahara-ku, Kawasaki-shi, Japan
Venue:
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Year:
2008

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Abstract

Statistical Timing Analysis (SSTA) is a method that calculates circuit delay statistically with process parameter variations, die-to-die (D2D) and within-die (WID) variations. In this paper, we model that WID parameter variations are independent for each cell and line in a chip and D2D variations are governed by one variation on a chip. We propose a new method of computing a full chip delay distribution considering both D2D and WID parameter variations. Experimental results show that the proposed method is more accurate than previous methods on actual chip designs.