First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Timing
Process and environmental variation impacts on ASIC timing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Block based statistical timing analysis with extended canonical timing model
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Robust extraction of spatial correlation
Proceedings of the 2006 international symposium on Physical design
Voltage binning under process variation
Proceedings of the 2009 International Conference on Computer-Aided Design
A linear statistical analysis for full-chip leakage power with spatial correlation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the 47th Design Automation Conference
Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
Existing static timing methodologies apply various techniques to address increasingly larger process variations. The techniques include multi-corner timing, on-chip variation (OCV) derating coefficients, and path-based common path pessimism removal (CPPR) procedures. These techniques, however, destroy the benefits of linear run-time and incrementality possessed by classical static timing. The major contribution of this work is an efficient statistical timing methodology with comprehensive modeling of process variations, while at the same time retaining those key benefits. Our methodology is compatible with existing characterization methods and scales well to large chip designs. To achieve this goal, three techniques are developed: (1) building the statistical delay model based on existing multi-corner library characterization; (2) modeling spatial correlation in a scalable manner; and (3) avoiding the time-consuming CPPR procedure by removing common path pessimism in the clock network by an incremental block-based technique. Experimental results on industrial 90 nm ASIC designs show that the proposed timing methodology correctly handles all types of process variation, achieves high correlation with traditional multi-corner timing with more than 4 x speedup, and is a vehicle for pessimism reduction.