The Design of Rijndael
A case study of partially evaluated hardware circuits: Key-specific DES
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A High Speed FPGA Implementation of the Rijndael Algorithm
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
| Hi-index | 0.00 |
Secure transmission of information is of interest to both public and private sectors. This is especially important with today's increased use of the internet for e-commerce. This research has been motivated by the need for high speed encryption algorithms for the applications that are independent of a particular algorithm and security standards. In this paper, hardware modeling and simulation of the common primitive operations used by the block ciphers are presented. The primitive operations were selected from the five finalist algorithms of the Advanced Encryption Standard (AES [1]) contest. These algorithms are promising for the selection of the new Encryption Standard, which was to replace the Data Encryption Standard (DES). As Field Programmable Gate Arrays (FPGAs) offer high flexibility and a low cost alternative for implementing these algorithms in Application-Specific Integrated Circuits (ASIC), these primitive operations are implemented in an Altera FPGA to permit user-programmable alternatives for a different encryption/decryption algorithm as opposed to a preselected one by a manufacturer. The results of implementing the Rijndael algorithm using these primitive operations also are presented.