VariaSim: simulating circuits and systems in the presence of process variability

Authors:
Bogdan F. Romanescu;Michael E. Bauer;Sule Ozev;Daniel J. Sorin
Affiliations:
Duke University;Duke University;Duke University;Duke University
Venue:
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Year:
2007

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Abstract

In this paper, we present VariaSim, the publicly available Static Statistical Timing Analysis (SSTA) Tool from Duke University. VariaSim enables researchers to analyze the impact of CMOS process variability on the behavior of circuits and systems.