Microprocessor Architectures: From VLIW to Tta
Microprocessor Architectures: From VLIW to Tta
On Limits of Wireless Communications in a Fading Environment when UsingMultiple Antennas
Wireless Personal Communications: An International Journal
A different approach to high performance computing
HIPC '97 Proceedings of the Fourth International Conference on High-Performance Computing
Trellis and Turbo Coding
Space-Time Wireless Systems: From Array Processing to MIMO Communications
Space-Time Wireless Systems: From Array Processing to MIMO Communications
Efficient detection algorithms for MIMO channels: a geometrical approach to approximate ML detection
IEEE Transactions on Signal Processing
On the sphere-decoding algorithm I. Expected complexity
IEEE Transactions on Signal Processing - Part I
IEEE Transactions on Signal Processing - Part I
On maximum-likelihood detection and the search for the closest lattice point
IEEE Transactions on Information Theory
From theory to practice: an overview of MIMO space-time coded wireless systems
IEEE Journal on Selected Areas in Communications
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Reconfigurable real-time MIMO detector on GPU
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Implementation of a High Throughput Soft MIMO Detector on GPU
Journal of Signal Processing Systems
High-throughput soft-output MIMO detector based on path-preserving trellis-search algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Novel detector implementations for 3G LTE downlink and uplink
Analog Integrated Circuits and Signal Processing
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Multiple-input multiple-output (MIMO) technology enables higher transmission capacity without additional frequency spectrum and is becoming a part of many wireless system standards. Sphere detection has been introduced in MIMO systems to achieve maximum likelihood (ML) or near-ML estimation with reduced complexity. This paper reviews related work on sphere detector implementations and presents an application-specific instruction set processor (ASIP) implementation of K-best list sphere detector (LSD) using transport triggered architecture (TTA). The implementation is based on using memory and heap data structure for symbol vector sorting. The design space is explored by presenting several variations of the implementation and comparing them with each other in terms of their latencies and hardware complexities. An early proposal for a parallelized architecture with a decoding throughput of approximately 5.3 Mbps is presented.