Parallel buffers for chip multiprocessors

  • Authors:
  • John Cieslewicz;Kenneth A. Ross;Ioannis Giannakakis

  • Affiliations:
  • Columbia University;Columbia University;Columbia University

  • Venue:
  • DaMoN '07 Proceedings of the 3rd international workshop on Data management on new hardware
  • Year:
  • 2007

Quantified Score

Hi-index 0.00

Visualization

Abstract

Chip multiprocessors (CMPs) present new opportunities for improving database performance on large queries. Because CMPs often share execution, cache, or bandwidth resources among many hardware threads, implementing parallel database operators that efficiently share these resources is key to maximizing performance. A crucial aspect of this parallelism is managing concurrent, shared input and output to the parallel operators. In this paper we propose and evaluate a parallel buffer that enables intra-operator parallelism on CMPs by avoiding contention between hardware threads that need to concurrently read or write to the same buffer. The parallel buffer handles parallel input and output coordination as well as load balancing so individual operators do not need to reimplement that functionality.